diff -crN --exclude build m5_1.0_beta1-clean/m5/arch/alpha/isa_desc m5_1.0_beta1/m5/arch/alpha/isa_desc
*** m5_1.0_beta1-clean/m5/arch/alpha/isa_desc	Sat Oct 18 03:02:29 2003
--- m5_1.0_beta1/m5/arch/alpha/isa_desc	Wed Dec 17 12:00:09 2003
***************
*** 1392,1397 ****
--- 1392,1399 ----
        protected:
  	int palFunc;	///< Function code part of instruction
  	int palOffset;	///< Target PC, offset from IPR_PAL_BASE
+ 	bool palValid;	///< is the function code valid?
+ 	bool palPriv;	///< is this call privileged?
  
  	/// Constructor.
  	CallPalBase(const char *mnem, MachInst _machInst,
***************
*** 1399,1407 ****
  	    : AlphaStaticInst(mnem, _machInst, __opClass),
  	      palFunc(PALFUNC)
  	{
! 	    int palPriv = ((machInst & 0x80) != 0);
! 	    int shortPalFunc = (machInst & 0x3f);
! 	    palOffset = 0x2001 + (palPriv << 12) + (shortPalFunc << 6);
  	}
  
  	std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
--- 1401,1422 ----
  	    : AlphaStaticInst(mnem, _machInst, __opClass),
  	      palFunc(PALFUNC)
  	{
! 	    // From the 21164 HRM (paraphrased):
! 	    // Bit 7 of the function code (mask 0x80) indicates
! 	    // whether the call is privileged (bit 7 == 0) or
! 	    // unprivileged (bit 7 == 1).  The privileged call table
! 	    // starts at 0x2000, the unprivielged call table starts at
! 	    // 0x3000.  Bits 5-0 (mask 0x3f) are used to calculate the
! 	    // offset.
! 	    const int palPrivMask = 0x80;
! 	    const int palOffsetMask = 0x3f;
! 
! 	    // Pal call is invalid unless all other bits are 0
! 	    palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
! 	    palPriv = ((machInst & palPrivMask) == 0);
! 	    int shortPalFunc = (machInst & palOffsetMask);
! 	    // Add 1 to base to set pal-mode bit
! 	    palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
  	}
  
  	std::string generateDisassembly(Addr pc, const SymbolTable *symtab)
***************
*** 2331,2348 ****
  
  #ifdef FULL_SYSTEM
      0x00: CallPal::call_pal({{
! 	// check to see if simulator wants to do something special
! 	// on this PAL call (including maybe suppress it)
! 	bool dopal = xc->simPalCheck(palFunc);
! 
! 	Annotate::Callpal(xc, palFunc);
  
- 	if (dopal) {
  	    if (!xc->misspeculating()) {
! 		AlphaISA::swap_palshadow(&xc->regs, true);
  	    }
- 	    xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
- 	    NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
  	}
      }});
  #else
--- 2346,2380 ----
  
  #ifdef FULL_SYSTEM
      0x00: CallPal::call_pal({{
! 	if (!palValid ||
! 	    (palPriv
! 	     && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
! 	    // invalid pal function code, or attempt to do privileged
! 	    // PAL call in non-kernel mode
! 	    fault = Unimplemented_Opcode_Fault;
! 	}
! 	else {
! 	    bool dopal = true;
  
  	    if (!xc->misspeculating()) {
! 		// check to see if simulator wants to do something special
! 		// on this PAL call (including maybe suppress it)
! 		dopal = xc->simPalCheck(palFunc);
! 
! 		Annotate::Callpal(xc, palFunc);
! 
! 		if (dopal) {
! 		    AlphaISA::swap_palshadow(&xc->regs, true);
! 		    xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC);
! 		}
! 	    }
! 
! 	    // if we're misspeculating, it's still safe (if
! 	    // unrealistic) to set NPC, as the control-flow change
! 	    // won't get committed.
! 	    if (dopal) {
! 		NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
  	    }
  	}
      }});
  #else
diff -crN --exclude build m5_1.0_beta1-clean/m5/base/loader/elf_object.cc m5_1.0_beta1/m5/base/loader/elf_object.cc
*** m5_1.0_beta1-clean/m5/base/loader/elf_object.cc	Sat Oct 18 03:02:29 2003
--- m5_1.0_beta1/m5/base/loader/elf_object.cc	Wed Dec 17 11:59:25 2003
***************
*** 83,89 ****
  	    textPhdrIdx = i;
  	    text.baseAddr = p->p_vaddr;
  	    text.size = p->p_filesz;
! 	    assert(p->p_filesz == p->p_memsz);
  	}
  	else {
  	    assert(p->p_flags & PF_R);
--- 83,90 ----
  	    textPhdrIdx = i;
  	    text.baseAddr = p->p_vaddr;
  	    text.size = p->p_filesz;
! 	    bss.baseAddr = text.baseAddr + text.size;
! 	    bss.size = p->p_memsz - p->p_filesz;
  	}
  	else {
  	    assert(p->p_flags & PF_R);
***************
*** 97,103 ****
  	}
      }
  
!     assert(foundText && foundData);
  
      DPRINTFR(Loader, "text: 0x%x %d\ndata: 0x%x %d\nbss: 0x%x %d\n",
  	     text.baseAddr, text.size, data.baseAddr, data.size,
--- 98,109 ----
  	}
      }
  
!     assert(foundText); 
! 
!     if(!foundData) {
! 	data.baseAddr = 0;
! 	data.size = 0;
!     }
  
      DPRINTFR(Loader, "text: 0x%x %d\ndata: 0x%x %d\nbss: 0x%x %d\n",
  	     text.baseAddr, text.size, data.baseAddr, data.size,
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/console.cc m5_1.0_beta1/m5/dev/console.cc
*** m5_1.0_beta1-clean/m5/dev/console.cc	Sat Oct 18 03:02:32 2003
--- m5_1.0_beta1/m5/dev/console.cc	Wed Dec 17 11:59:55 2003
***************
*** 49,54 ****
--- 49,56 ----
  #include "base/socket.hh"
  #include "base/trace.hh"
  #include "mem/functional_mem/memory_control.hh"
+ #include "dev/turbolaser.hh"
+ 
  
  using namespace std;
  
***************
*** 281,287 ****
      int old = _status;
      _status |= i;
      if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
!         intr->post(TheISA::INTLEVEL_IRQ0);
  }
  
  void
--- 283,289 ----
      int old = _status;
      _status |= i;
      if (MaskStatus(old, _enable) != MaskStatus(_status, _enable) && intr)
!         tlaser->post_interrupt(TheISA::INTLEVEL_IRQ0);
  }
  
  void
***************
*** 293,298 ****
--- 295,308 ----
      intr = i;
  }
  
+ 
+ void
+ SimConsole::initTlaser(Turbolaser *tl)
+ {
+   tlaser = tl;
+ }
+ 
+ 
  void
  SimConsole::setInt(int bits)
  {
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/console.hh m5_1.0_beta1/m5/dev/console.hh
*** m5_1.0_beta1-clean/m5/dev/console.hh	Sat Oct 18 03:02:27 2003
--- m5_1.0_beta1/m5/dev/console.hh	Wed Dec 17 11:59:55 2003
***************
*** 41,46 ****
--- 41,48 ----
  #include "base/socket.hh"
  #include "sim/sim_object.hh"
  
+ class Turbolaser;
+ 
  class ConsoleListener;
  class SimConsole : public SimObject
  {
***************
*** 100,107 ****
--- 102,112 ----
  
      // interrupt handle
      IntrControl *intr;
+     Turbolaser *tlaser;
  
    public:
+     void initTlaser(Turbolaser *tl);
+ 
      /////////////////
      // OS interface
  
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/etherdev.cc m5_1.0_beta1/m5/dev/etherdev.cc
*** m5_1.0_beta1-clean/m5/dev/etherdev.cc	Sat Oct 18 03:02:27 2003
--- m5_1.0_beta1/m5/dev/etherdev.cc	Wed Dec 17 11:59:55 2003
***************
*** 49,54 ****
--- 49,55 ----
  #include "cpu/exec_context.hh"
  #include "targetarch/vtophys.hh"
  #include "sim/sim_stats.hh"
+ #include "dev/turbolaser.hh"
  
  using namespace std;
  
***************
*** 524,530 ****
  {
      if (!cpuPendingIntr) {
  	cpuPendingIntr = true;
! 	intctrl->post(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET);
      }
  }
  
--- 525,531 ----
  {
      if (!cpuPendingIntr) {
  	cpuPendingIntr = true;
! 	tlaser->post_interrupt(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET);
      }
  }
  
***************
*** 949,954 ****
--- 950,963 ----
      return true;
  }
  
+ 
+ void
+ EtherDev::initTlaser(Turbolaser *tl)
+ {
+   tlaser = tl;
+ }
+ 
+ 
  void
  EtherDev::transferDone()
  {
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/etherdev.hh m5_1.0_beta1/m5/dev/etherdev.hh
*** m5_1.0_beta1-clean/m5/dev/etherdev.hh	Sat Oct 18 03:02:28 2003
--- m5_1.0_beta1/m5/dev/etherdev.hh	Wed Dec 17 11:59:55 2003
***************
*** 82,87 ****
--- 82,88 ----
  class IntrControl;
  class EtherDevInt;
  class PhysicalMemory;
+ class Turbolaser;
  
  /*
   * Ethernet device model
***************
*** 172,177 ****
--- 173,179 ----
  
    protected:
      IntrControl *intctrl;
+     Turbolaser *tlaser;
      bool txEnable;
      bool rxEnable;
      Tick txDelay;
***************
*** 244,249 ****
--- 246,254 ----
  
      void setInterface(EtherDevInt *i) { assert(!interface); interface = i; }
  
+ 
+     void initTlaser(Turbolaser *tl);
+ 
    public:
      void regStats();
  
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/scsi_ctrl.cc m5_1.0_beta1/m5/dev/scsi_ctrl.cc
*** m5_1.0_beta1-clean/m5/dev/scsi_ctrl.cc	Sat Oct 18 03:02:26 2003
--- m5_1.0_beta1/m5/dev/scsi_ctrl.cc	Wed Dec 17 11:59:55 2003
***************
*** 36,41 ****
--- 36,43 ----
  #include "dev/pcireg.h"
  #include "mem/functional_mem/memory_control.hh"
  
+ #include "dev/turbolaser.hh"
+ 
  using namespace std;
  
  ScsiController::ScsiController(const string &name, DmaEngine *de,
***************
*** 194,200 ****
  {
      pending = (num_in_progress > 0);
      if (pending)
! 	intctrl->post(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_SCSI);
  }
  
  void
--- 196,202 ----
  {
      pending = (num_in_progress > 0);
      if (pending)
! 	tlaser->post_interrupt(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_SCSI);
  }
  
  void
***************
*** 210,215 ****
--- 212,225 ----
  { return pending; }
  
  
+ void
+ ScsiController::initTlaser(Turbolaser *tl)
+ {
+   tlaser = tl;
+ }
+ 
+ 
+ 
  BEGIN_DECLARE_SIM_OBJECT_PARAMS(ScsiController)
  
      SimObjectParam<DmaEngine *> engine;
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/scsi_ctrl.hh m5_1.0_beta1/m5/dev/scsi_ctrl.hh
*** m5_1.0_beta1-clean/m5/dev/scsi_ctrl.hh	Sat Oct 18 03:02:30 2003
--- m5_1.0_beta1/m5/dev/scsi_ctrl.hh	Wed Dec 17 11:59:55 2003
***************
*** 69,74 ****
--- 69,75 ----
  class IntrControl;
  class ScsiDevice;
  class DiskImage;
+ class Turbolaser;
  
  /*
   * Device model for a very simple SCSI controller
***************
*** 86,91 ****
--- 87,93 ----
    protected:
      DmaEngine *dma;
      IntrControl *intctrl;
+     Turbolaser *tlaser;
      ScsiData scsi_regs;
  
    protected:
***************
*** 103,107 ****
--- 105,111 ----
      void intr_post();
      void intr_clear();
      bool intr_pending();
+ 
+     void initTlaser(Turbolaser *tl);
  };
  #endif // __SCSI_CTRL_HH__
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/tlaser_clock.cc m5_1.0_beta1/m5/dev/tlaser_clock.cc
*** m5_1.0_beta1-clean/m5/dev/tlaser_clock.cc	Sat Oct 18 03:02:36 2003
--- m5_1.0_beta1/m5/dev/tlaser_clock.cc	Wed Dec 17 11:59:56 2003
***************
*** 114,121 ****
      for (int i = 0; i < size; i++){
  	if (!interrupting[i]) {
  	    interrupting[i] = true;
! 	    BaseCPU *cpu = xcvec[i]->cpu;
! 	    cpu->post_interrupt(TheISA::INTLEVEL_IRQ2, 0);
  	}
      }
  }
--- 114,121 ----
      for (int i = 0; i < size; i++){
  	if (!interrupting[i]) {
  	    interrupting[i] = true;
! 	    //BaseCPU *cpu = xcvec[i]->cpu;
! 	    tlaser->post_interrupt(TheISA::INTLEVEL_IRQ2, 0);
  	}
      }
  }
***************
*** 146,151 ****
--- 146,159 ----
      interrupting[1] = intr;
  }
  
+ 
+ void
+ TlaserClock::initTlaser(Turbolaser *tl)
+ {
+   tlaser = tl;
+ }
+ 
+ 
  BEGIN_DECLARE_SIM_OBJECT_PARAMS(TlaserClock)
  
    SimObjectParam<IntrControl *> intr_control;
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/tlaser_clock.hh m5_1.0_beta1/m5/dev/tlaser_clock.hh
*** m5_1.0_beta1-clean/m5/dev/tlaser_clock.hh	Sat Oct 18 03:02:35 2003
--- m5_1.0_beta1/m5/dev/tlaser_clock.hh	Wed Dec 17 11:59:56 2003
***************
*** 41,46 ****
--- 41,47 ----
  #include "sim/sim_object.hh"
  
  class IntrControl;
+ class Turbolaser;
  /*
   * Device model for a hardware interrupt timer
   */
***************
*** 70,75 ****
--- 71,77 ----
      bool interrupting[12/*MAX_CPUS*/];
  
      IntrControl *intrctrl;
+     Turbolaser *tlaser;
  
    public:
      TlaserClock(const std::string &name, IntrControl *i, Tick frequency,
***************
*** 84,89 ****
--- 86,93 ----
      virtual void serialize();
      virtual void unserialize(IniFile &db, const std::string &category,
  			     ConfigNode *node);
+ 
+     void initTlaser(Turbolaser *tl);
  };
  
  #endif // __TLASER_CLOCK_HH__
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/tlaser_ipi.cc m5_1.0_beta1/m5/dev/tlaser_ipi.cc
*** m5_1.0_beta1-clean/m5/dev/tlaser_ipi.cc	Sat Oct 18 03:02:30 2003
--- m5_1.0_beta1/m5/dev/tlaser_ipi.cc	Wed Dec 17 11:59:56 2003
***************
*** 81,88 ****
  			tlaser->ipi_pending[i] + 1, req->cpu_num);
  
  		if (!tlaser->ipi_pending[i]) {
! 		    BaseCPU *cpu = xcvec[i]->cpu;
! 		    cpu->post_interrupt(TheISA::INTLEVEL_IRQ2, 1);
  		}
  
  		tlaser->ipi_pending[i]++;
--- 81,88 ----
  			tlaser->ipi_pending[i] + 1, req->cpu_num);
  
  		if (!tlaser->ipi_pending[i]) {
! 		  //BaseCPU *cpu = xcvec[i]->cpu;
! 		    tlaser->post_interrupt(TheISA::INTLEVEL_IRQ2, 1);
  		}
  
  		tlaser->ipi_pending[i]++;
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/tlaser_node.cc m5_1.0_beta1/m5/dev/tlaser_node.cc
*** m5_1.0_beta1-clean/m5/dev/tlaser_node.cc	Sat Oct 18 03:02:32 2003
--- m5_1.0_beta1/m5/dev/tlaser_node.cc	Wed Dec 17 11:59:56 2003
***************
*** 40,45 ****
--- 40,48 ----
      ExecContext *xc = req->xc;
      int cpuid = xc->cpu_id;
  
+     if(cpuid != 0)
+       panic("blah\n");
+ 
      switch (req->size) {
        case sizeof(uint32_t):
  	switch(daddr) {
***************
*** 141,149 ****
--- 144,162 ----
  		panic("Turbolaser: spurious interrupt\n");
  	    }
  
+ 
  	    *(uint32_t *)data = reg;
+ 	    
  	    return No_Fault;
  
+ 
+ 	case TLINTRMASK0_REG:
+ 	  *(uint32_t *)data = tlaser->intr_mask_type[cpuid];
+ 	  return No_Fault;
+ 	case TLINTRMASK1_REG:
+ 	  *(uint32_t *)data = tlaser->intr_mask_type[cpuid];
+ 	  return No_Fault;
+ 
  	  case IDPNSE0_REG: // 0x2a40
  	    DPRINTF(Regs, "TlaserNode(%d): EMPTY READ daddr=%#x\n",
  		    number, daddr);
***************
*** 295,300 ****
--- 308,325 ----
  		panic("wrong cpu!\n");
  	    tlaser->intr_sum_type[cpuid] = *(uint64_t *)data;
  	    return No_Fault;
+ 	case TLINTRMASK0_REG:
+ 	  if((cpuid % 2) != 0)
+ 	    panic("wrong cpu!\n");
+ 	  tlaser->intr_mask_type[cpuid] = *(uint64_t *)data;
+ 	  tlaser->maskChanged(cpuid);
+ 	  return No_Fault;
+ 	case TLINTRMASK1_REG:
+ 	  if ((cpuid % 2) != 1)
+ 	    panic("wrong cpu!\n");
+ 	  tlaser->intr_mask_type[cpuid] = *(uint64_t *)data;
+ 	  tlaser->maskChanged(cpuid);
+ 	  return No_Fault;
  #if 0
  	  case TLMBPR_REG:
  	    DPRINTF(Regs, "TlaserNode(%d): EMPTY WRITE daddr=%#x size=%d\n",
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/turbolaser.cc m5_1.0_beta1/m5/dev/turbolaser.cc
*** m5_1.0_beta1-clean/m5/dev/turbolaser.cc	Sat Oct 18 03:02:37 2003
--- m5_1.0_beta1/m5/dev/turbolaser.cc	Wed Dec 17 11:59:56 2003
***************
*** 53,63 ****
        clock(c), ipi(i), mbox(m), interrupt_frequency(intr_freq)
  {
      ipi->setTurbolaser(this);
      int size = ic->cpu->system->xcvec.size();
!     for (int i = 0; i < size; i++)
  	intr_sum_type[i] = ipi_pending[i] = 0;
  }
  
  BEGIN_DECLARE_SIM_OBJECT_PARAMS(Turbolaser)
  
      SimObjectParam<ScsiController *> scsi;
--- 53,143 ----
        clock(c), ipi(i), mbox(m), interrupt_frequency(intr_freq)
  {
      ipi->setTurbolaser(this);
+     clock->initTlaser(this);
+     cons->initTlaser(this);
+     ethernet->initTlaser(this);
+     scsi->initTlaser(this);
      int size = ic->cpu->system->xcvec.size();
!     for (int i = 0; i < size; i++) {
  	intr_sum_type[i] = ipi_pending[i] = 0;
+ 	intr_mask_type[i] = 0xffffffff;
+     }
  }
  
+ 
+ #define IS_CONSOLE(x,y) ( ((x) == TheISA::INTLEVEL_IRQ0) && ((y) == 0) )
+ #define IS_CLOCK(x,y) ( ((x) == TheISA::INTLEVEL_IRQ2) && ((y) == 0) )
+ #define IS_IPI(x,y) ( ((x) == TheISA::INTLEVEL_IRQ2) && ((y) == 1) )
+ #define IS_IPL15(x,y) ( ((x) == TheISA::INTLEVEL_IRQ1) )
+ 
+ 
+ 
+ void
+ Turbolaser::post_interrupt(int num, int index)
+ {
+ 
+   int cpuid = 0;  // will this work (FIXME)
+ 
+   if(cpuid != 0)
+     panic("somethings wrong...\n");
+ 
+   //do interupt masking here??
+   if(IS_CONSOLE(num,index) && !(intr_mask_type[cpuid]& (1 << 0)))   
+     return;
+   
+   if(IS_CLOCK(num,index) && !(intr_mask_type[cpuid] & (1 << 6)))
+     return;
+ 
+   if(IS_IPI(num,index) && !(intr_mask_type[cpuid] & (1 << 5)))
+     return;
+ 
+   if(IS_IPL15(num,index) && !(intr_mask_type[cpuid] & (1<<2))) 
+     return;
+     
+   intctrl->post(num,index);
+ 
+ }
+ 
+ 
+ 
+ #define IS_CONSOLE_MASK(x) ( (x) & (1 << 0) )
+ #define IS_CLOCK_MASK(x) ( (x) & (1 << 6) )
+ #define IS_IPI_MASK(x) ( (x) & (1 << 5) )
+ #define IS_IPL15_MASK(x) ( (x) & (1 << 2) )
+ 
+ 
+ 
+ void
+ Turbolaser::maskChanged(int cpuid)
+ {
+   int newmask = intr_mask_type[cpuid];
+ 
+   if(IS_CONSOLE_MASK(newmask))
+     if(cons->intStatus())
+       intctrl->post(TheISA::INTLEVEL_IRQ0);
+ 
+   if(IS_CLOCK_MASK(newmask))
+     if(clock->pending(cpuid))
+       intctrl->post(TheISA::INTLEVEL_IRQ2, 0);
+ 
+   if(IS_IPI_MASK(newmask))
+     if(ipi_pending[cpuid])
+       intctrl->post(TheISA::INTLEVEL_IRQ2, 1);
+ 
+   if(IS_IPL15_MASK(newmask)) {
+     if(ethernet->cpuIntrPending())
+       intctrl->post(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET);
+     if(scsi->intr_pending())
+       intctrl->post(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_SCSI);
+   }
+     
+ }
+ 
+ 
+ 
+ 
+ 
+ 
  BEGIN_DECLARE_SIM_OBJECT_PARAMS(Turbolaser)
  
      SimObjectParam<ScsiController *> scsi;
diff -crN --exclude build m5_1.0_beta1-clean/m5/dev/turbolaser.hh m5_1.0_beta1/m5/dev/turbolaser.hh
*** m5_1.0_beta1-clean/m5/dev/turbolaser.hh	Sat Oct 18 03:02:28 2003
--- m5_1.0_beta1/m5/dev/turbolaser.hh	Wed Dec 17 11:59:56 2003
***************
*** 45,50 ****
--- 45,52 ----
  class EtherDev;
  class Turbolaser : public SimObject
  {
+  
+ 
    public:
      IntrControl *intctrl;
  //    ConsoleListener *listener;
***************
*** 58,63 ****
--- 60,66 ----
      TlaserMBox *mbox;
  
      int intr_sum_type[12/*MAX_CPUS*/];
+     int intr_mask_type[12/*MAX_CPUS*/];
      int ipi_pending[12/*MAX_CPUS*/];
  
      int interrupt_frequency;
***************
*** 67,72 ****
--- 70,87 ----
  	       EtherDev *ethernet, TlaserClock *clock, TlaserIpi *ipi,
  	       TlaserMBox *mbox, SimConsole *, IntrControl *intctrl,
  	       int intrFreq);
+ 
+     
+     void maskChanged(int cpuid);
+ 
+     void post_interrupt(int num, int index = 0);
+ 
  };
  
+ 
+ 
+ 
+ 
+ 
+ 
  #endif // __TURBOLASER_HH__
diff -crN --exclude build --exclude decoder.cc m5_1.0_beta1-clean/m5/kern/tru64/tru64_system.cc m5_1.0_beta1/m5/kern/tru64/tru64_system.cc
*** m5_1.0_beta1-clean/m5/kern/tru64/tru64_system.cc	Sat Oct 18 03:02:28 2003
--- m5_1.0_beta1/m5/kern/tru64/tru64_system.cc	Mon Jan 19 11:37:07 2004
***************
*** 63,70 ****
      if (console == NULL)
    	fatal("Could not load console file %s", console_path);
  
!     if (!kernel->loadGlobalSymbols(kernelSymtab))
!  	panic("could not load kernel symbols\n");
  
      if (!console->loadGlobalSymbols(consoleSymtab))
   	panic("could not load console symbols\n");
--- 63,70 ----
      if (console == NULL)
    	fatal("Could not load console file %s", console_path);
  
! //    if (!kernel->loadGlobalSymbols(kernelSymtab))
! // 	panic("could not load kernel symbols\n");
  
      if (!console->loadGlobalSymbols(consoleSymtab))
   	panic("could not load console symbols\n");
***************
*** 133,148 ****
  
      if (kernelSymtab->findAddress("panic", addr))
  	kernelPanicEvent->schedule(addr);
!     else
! 	panic("could not find kernel symbol \'panic\'");
  
      if (consoleSymtab->findAddress("panic", addr))
  	consolePanicEvent->schedule(addr);
  
      if (kernelSymtab->findAddress("badaddr", addr))
  	badaddrEvent->schedule(addr);
!     else
! 	panic("could not find kernel symbol \'badaddr\'");
  
      if (kernelSymtab->findAddress("tl_v48_capture_power_state", addr))
  	skipPowerStateEvent->schedule(addr);
--- 133,148 ----
  
      if (kernelSymtab->findAddress("panic", addr))
  	kernelPanicEvent->schedule(addr);
! //    else
! //	panic("could not find kernel symbol \'panic\'");
  
      if (consoleSymtab->findAddress("panic", addr))
  	consolePanicEvent->schedule(addr);
  
      if (kernelSymtab->findAddress("badaddr", addr))
  	badaddrEvent->schedule(addr);
! //    else
! //	panic("could not find kernel symbol \'badaddr\'");
  
      if (kernelSymtab->findAddress("tl_v48_capture_power_state", addr))
  	skipPowerStateEvent->schedule(addr);